Digital Verification Specialist
1 day ago
We are seeking a skilled ASIC Digital Verification Engineer to join our team. As a key member of our digital verification group, you will be responsible for developing and maintaining SystemVerilog-based verification environments for SoC-level and subsystem-level validation.
Key Responsibilities:
- Design and implement SystemVerilog-based verification environments for complex SoC designs.
- Develop UVM-based testbenches and verification components to simulate functional behavior.
- Collaborate with design, architecture, and DV teams to ensure full functional coverage of digital IP blocks.
- Create and execute directed and constrained-random test cases.
- Analyze waveforms and debug simulation failures across RTL and gate-level simulations.
- Automate test regressions and generate functional coverage reports.
Requirements:
- Bachelor's or Master's degree in Electrical or Computer Engineering.
- 4+ years of hands-on experience in ASIC digital verification.
- Strong knowledge of SystemVerilog, UVM, and digital design concepts.
- Experience verifying SoC-level designs, including bus protocols, peripherals, and memory interfaces.
- Background in networking, display, or mixed-signal SoC designs is a strong plus.
- Proficiency in Python scripting for test automation and tooling.
- Familiarity with industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Siemens Questa).
- Excellent debugging and communication skills.
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